• What are the various design changes you do to meet design power targets?
  Ans: Design with Multi-VDD designs, Areas which requires high performance, goes with high VDD and areas which needs low-performance are working with low Vdd's, by creating Voltage-islands and making sure that appropriate level-shifters are placed in the cross-voltage domains Designing with Multi-Vt's(threshold voltages), areas which require high performance, goes with low Vt, but takes lot of leakage current, and areas which require low performance with high Vt cells, which has low leakage numbers, by incorporating this design process, we can reduce the leakage power. As in the design , clocks consume more amount of power, placing optimal clock-gating cells, in the design and controlling them by the module enable's gives a lot of power-savings.
  As clock-tree's always switch making sure that most number of clock-buffers are after the clock-gating cells, this reduces the switching there by power-reduction.
  Incorporating Dynamic Voltage and Frequency scaling (DVFS) concepts based on the application , there by reducing the systems voltage and frequency numbers when the application does not require to meet the performance targets. Ensure the design with IR-Drop analysis and ground-bounce analysis, is with-in the design specification requirement. Place power-switches, so that the leakage power can be reduced. related information.
• what is meant by Library Characterizing
  Ans: Characterization in terms of delay, power consumption,..
• what is meant by wireload model
  Ans: In the synthesis tool, in order to model the wires we use a concept called as "Wireload models", Now the question is what is wireload models: Wireload models are statistical based on models with respect to fanout. say for a particular technology based on our previous chip experience we have a rough estimate we know if a wire goes for "n" number of fanin then we estimate its delay as say "x" delay units. So a model file is created with the fanout numbers and corresponding estimated delay values. This file is used while performing Synthesis to estimate the delay for Wires, and to estimate the delay for cells, technology specific library model files will be available
• what are the measures to be taken to design for optimized area
  Ans: As silicon real-estate is very costly and saving is directly propotional to the company's revenue generation lot of emphasize is to design which has optimial utilization in the area-front. The steps to reduce area are
  If the path is not timing-critical, then optimize the cells to use the low-drive strength cells so that there will saving in the area. Abut the VDD rows Analyzing the utilization numbers with multiple floor-planning versions which brings up with optimized area targets.
• what all will you be thinking while performing floorplan
  Ans: Study the data-flow graph of the design and place the blocks accordingly, to reducing the weighted sum of area, wire-length. Minimize the usuage of blocks other-than square shapes, having notches Place the blocks based on accessibility/connectivity, thereby reducing wire-length. Abut the memory, if the pins are one-sided, there-by area could be reduced. If the memory communicates to the outside world more frequently , then placing at the boundary makes much of a sense. Study the number of pins to be routed, with the minimum metal width allowed , estimate the routability issues. Study the architecture and application , so that the blocks which will be enabled should be scattered, to reduce the power-ground noise.
• what are the measures in the Design taken for Meeting Signal-integrity targets
  Ans: As more and more devices are getting packed, results in more congested areas, and coupling capactiances dominating the wire-capacitance, creates SI violations. Let's see now by what are all the measures we can reduce/solve it.
  As clock-tree runs across the whole chip, optimizing the design for SI, is essential route the clock with double-pitch and triple spacing. In-case of SI violation, spacing the signal nets reduces cross-talk impacts.
  Shield the nets with power-nets for high frequency signal nets to prevent from SI.
  Enable SI aware routing , so that the tool takes care for SI
  Ensure SI enabled STA runs, and guarantee the design meeting the SI requirements
  Route signals on different layers orthogonal to each other
  Minimize the parallel run-length wires, by inserting buffers.
• what are the measures taken in the Design achieving better Yield
  Ans: Better yield could be achieved by reducing the possibility of manufacturability flaws. Guaranting the circuit performance, by reducing parametric yield, with process variations playing a major role is a big-challenge.
  Create more powerful stringent runset files with pessimistic spacing/short rules.
  Check for the areas where the design is prone to lithographic issues, like sharp cuts and try to re-route it.
  For via-reliability issues, use redundant vias, to reduce the chances for via-breakage.
  In order to design for yield-enhancement , design systems, which could have optimal redundancy, like repairable memories.
  Optimal placing of de-coupling capacitances, reduces the power-surges.
  Doubling the width of the non-critical nets, clock-nets can increase the yield parameter.
  Ensure that the poly-orientation are maintained.
• what are the measures or precautions to be taken in the Design when the chip has both analog and digital portions
  Ans: Designing for Optimal integration of Analog and Digital As today's IC has analog components also inbuilt , some design practices are required for optimal integration. Ensure in the floorplanning stage that the analog block and the digital block are not siting close-by, to reduce the noise. Ensure that there exists seperate ground for digital and analog ground to reduce the noise. Place appropriate guard-rings around the analog-macro's. Incorporating in-built DAC-ADC converters, allows us to test the analog portion using digital testers in an analog loop-back fashion. Perform techniques like clock-dithering for the digital portion.
• what are the steps incorporated for Engineering Change Order[ECO]
  Ans: As more and more complex the IC design is , and with lot of first time application , is more prone to last minute changes, there should be provision in the design-flow to accomodate the functional and timing bugs. The step to perform this called as Engineering change order(ECO). Ensure that the design has spare functional gates well distributed across the layout. Ensure that the selection the spare gates, has many flavours of gates and universal gates, so that any functionality could be achieved.
• what are the steps performed to achieve Lithography friendly Design
  Ans: Designing for Manufacturability requires validating the design full-filling lithography rules Checking the layout confirming the design rules (spacing,trace-width,shorts). Check for the less-congested areas and increasing the spacing of the nets.
• what does synthesis mean
  Ans: Synthesis is a step of mapping the RTL files (verilog format or vhdl format) to convert it to the technology specific cells..
• What are the various ways to reduce Clock Insertion Delay in the Design
  Ans: 1. Number of Clock sinks
  2. Balancing two different clock frequencies
  3. Placement of clock sinks.
  4. Placement of Clock gating cells
  5. Clock tree buffers/inverters drive strength's
  6. Clock Transition
  7. placement of Clockgating cells and the clock sinks
  8. Combinationals cells in the path of clocks (say clock dividers, muxes, clockgates) ...
• what are the various functional verification methodologies
  Ans: TLM(Transaction Level Modelling)
  Linting
  RTL Simulation ( Enivronment involving : stimulus generators, monitors, response checkers, transactors)
  Gate level Simulation
  Mixed-signal simulations
  Regression
• What does formal verification mean?
  Ans: Formal verification uses Mathematical techniquest by prooving the design through assertions or properties. Correctness of the design can be achieved through assertions with out the necessity for simulations. The methods of formal verification are
  1. Equivalence checking In this method of checking the designs are compared based on mathematical equations and compared whether they are equal or not . Original RTL vs Modified RTL RTL vs Netlist Golden Netlist vs Modified/Edited Netlist Synthesis Netlist vs Place and route Netlist Remember : Formal verification doesnt check for functionality of the RTL code. It will be only checking the equivalence.
  2. Model checking Property specification languages like PSL or SVA, are formally analyzed to see if they are always true for a design. This can exhaustively prove if a property is correct, but does tend to suffer from state-space explosion: the time to analyse a design is directly propotional to the amount of states.

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