设计一个简易的电子琴，可通过按键输入来控制音响。演奏时可选择用键盘演奏还是自动演奏已存入的乐曲，能够演奏多首乐曲，而且每首乐曲可重复演奏。VHDL语言如下：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity auto is
port ( clk:in std_logic;
      auto: in std_logic;
      clk2: buffer std_logic;
      index2: in std_logic_vector(7 downto 0) ;
     index0: out std_logic_vector (7 downto 0 ));
end auto;
architecture behavioral of auto is
 signal count0:integer range 0 to 31;
begin
pulse0: process( clk,auto)
variable count :integer range 0 to 8;
begin
    if auto='1' then
count:=0;clk2<='0' ;
elsif (clk'event and clk='1')then
  count:=count+1;
  if count= 4 then
   clk2<='1';
  elsif count="8" then
  clk2<='0';count:=0;
  end if;
 end if;
end process;
music:process(clk2)
  begin
  if(clk2'event and clk2='1')then
     if(count0=31)then
       count0<=0;
      else
       count0<=count0+1;
       end if;
    end if;
 end process;
 com1 :process(count0,auto,index2)
 begin
  if auto='0' then
    case count0 is
         when 0=>index0<="00000100";
          when 1=>index0<="00000100";--3
        when 2=>index0<="00000100";--3
 when 3=>index0<="00000100";--3
when 4=>index0<="00001000";
when 5=>index0<="00001000";--3
when 6=>index0<="00001000";--3
when 7=>index0<="00010000";--3
when 8=>index0<="10000000";--3
when 9=>index0<="10000000";--3
when 10=>index0<="10000000";--3
when 11=>index0<="00000100";--3
when 12=>index0<="00000010";--3
when 13=>index0<="00000010";--3
when 14=>index0<="00000001";--3
when 15=>index0<="00000001";--3
when 16=>index0<="00010000";--3
when 17=>index0<="00010000";--3
when 18=>index0<="00001000";--3
when 19=>index0<="00001000";--3
when 20=>index0<="00001000";--3
when 21=>index0<="00000100";--3、
when 22=>index0<="00000010";--3
when 23=>index0<="00000010";--3
when 24=>index0<="00010000";--3
when 25=>index0<="00010000";--3
when 26=>index0<="00001000";--3
when 27=>index0<="00001000";--3
when 28=>index0<="00000100";--3
when 29=>index0<="00000100";--3
when 30=>index0<="00000010";--3
when 31=>index0<="00000010";--3
when others => null;
end case;
else index0 <= index2;
end if;
 end process;
end behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tone is
  port( index :in std_logic_vector(7 downto 0);
       code:  out std_logic_vector(6 downto 0);
       high: out std_logic;
        tone0: out integer range 0 to 2047);
 end tone;
architecture art of tone is
  begin
search: process(index)
  begin
  case index is
  when "00000001"=> tone0<=773;code<="1001111";high<='1';
when "00000010"=> tone0<=912;code<="0010010";high<='1';
when "00000100"=> tone0<=1036;code<="0000110";high<='1';
when "00001000"=> tone0<=1116;code<="1001100";high<='1';
when "00010000"=> tone0<=1197;code<="0100100";high<='1';
when "00100000"=> tone0<=1290;code<="0100000";high<='0';
when "01000000"=> tone0<=1372;code<="0001111";high<='0';
when "10000000"=> tone0<=1410;code<="0000000";high<='0';
when others=> tone0<=2047;code<="0000001";high<='0';
end case;
end process;
end art;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
  port(clk1:in std_logic;
       tone1:in integer range 0 to 2047;
       spks:out std_logic);
end entity fenpin;
architecture art of fenpin is
  signal preclk:std_logic;
  signal fullspks:std_logic;
begin
process(clk1)
  variable count:integer range 0 to 8;
begin
  if(clk1'event and clk1='1')then
      count:=count+1;
      if count="2" then
        preclk<='1';
elsif count="4" then
   preclk<='0';count:=0;
  end if
end process;
process(preclk,tone1)
   variable count11:integer range 0 to 2047;
   begin
    if(preclk'event and preclk='1')then
       if count11<tone1 then
          count11:=count11+1;fullspks<='1';
        else
           count11:=0;fullspks<='0';
        end if;
     end if;
 end process;
process(fullspks)
   variable count2:std_logic:='0';
   begin
     if(fullspks'event and fullspks='1')then
         count2:=not count2;
         if count2='1' then
           spks<='1';
          else
          spks<='0';
         end if;
      end if;
  end process;
end art;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dianziqin is
   port( clk32mhz: in std_logic;
         handtoauto: in std_logic;
         code1: out std_logic_vector(6 downto 0);
         index1: in std_logic_vector (7 downto 0);
         high1: out std_logic;
         spkout: out std_logic);
end;
architecture art of dianziqin is
  component auto
  port( clk: in std_logic;
        auto: in std_logic;
        index2: in std_logic_ vector(7 downto 0);
        index0: out std_logic_vector(7 downto 0));
end component;
component tone
port( index: in std_logic_vector( 7 downto 0);
      code: out std_logic_vector(6 downto 0);
      high:  out std_logic;
      tone0:out integer range 0 to 2047);
end component;
component fenpin
 port(clk1: in std_logic;
      tone1:in integer range 0 to 2047;
      spks: out std_logic);
  end component;
signal tone2:integer range 0 to 2047;
signal indx :std_logic_vector(7 downto 0);
begin
u0:aut0 port map(clk=>clk32mhz,index2=>index1,index0=>indx,aut0=>handtoaut0);
u1: tone port map(index=>indx,tone0=>tone2,code=>code1,high=>high1);
u2:fenpin port map(clk1=>clk32mhz,tone1=>tone2,spks=>spkout);
end art;

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